$1)$ Connect and check the following circuit which implementsF$1$ and F$2,$ using $74138$ decoder and NAND gate. Record your data in table $2.$F$1=$ AC$($B $+$B$\text{'})+$ A'B'C' $=$ ABC $+$ AB'C $+$ A'B'C' $=$ M$7+$ M$5+$ M$0$F$2=$ A$\text{'}$B $($C $+$ C$\text{'})+$ AB'C' $=$ A'BC $+$ A'BC' $+$ AB'C' $=$ M$3+$ M$2+$ M$4-2-$ EENG$115/$INFE$115=========================$ Introduction to Logic DesignNOTE: The output is active low; inverters are connected to the output before using or gate. Invert OR $=$ NAND.Table $2$Enable InputG$2$A G$2$B G$1$ C B A F$1$ F$2001000001001001010001011001100001101001110001111$