1) Consider a base-line CMOS inverter but with the multiplier (M) for the PMOS device set to 3 (M=3). Show (through calculation) that the equivalent resistances (Req np) are now approximately equal in value. (5 pts) 2) Assume that it is required that the signal at the output of this gate be transmitted to a 250pF capacitive load. Calculate, and verify through PSpice simulation, the delay time, as estimated by the time constant (t), when this load is driven directly by the modified inverter. (20 pts) 1) Consider a base-line CMOS inverter but with the multiplier (M) for the PMOS device set to 3 (M=3). Show (through calculation) that the equivalent resistances (Req np) are now approximately equal in value. (5 pts) 2) Assume that it is required that the signal at the output of this gate be transmitted to a 250pF capacitive load. Calculate, and verify through PSpice simulation, the delay time, as estimated by the time constant (t), when this load is driven directly by the modified inverter. (20 pts)