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1. Consider the combinational logic circuit shown in Figure 1. Figure T a. How many possible single stuck-at faults does this circuit have? b. How
1. Consider the combinational logic circuit shown in Figure 1. Figure T a. How many possible single stuck-at faults does this circuit have? b. How many collapsed single stuck-at faults does this circuit have? 2. Find the vectors to detect the faults w/O, w/1 in the circuit shown in Figure 2. Figure 2 3. For the circuit in Figure 3, use the parallel-pattern single-fault propagation fault simulation technique to identify the test vectors to detect J/1, J/0, E/1, H/O faults. G4 G1 Figure 3 1. Consider the combinational logic circuit shown in Figure 1. Figure T a. How many possible single stuck-at faults does this circuit have? b. How many collapsed single stuck-at faults does this circuit have? 2. Find the vectors to detect the faults w/O, w/1 in the circuit shown in Figure 2. Figure 2 3. For the circuit in Figure 3, use the parallel-pattern single-fault propagation fault simulation technique to identify the test vectors to detect J/1, J/0, E/1, H/O faults. G4 G1 Figure 3
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