1. Consider the one-cycle (non-pipelined) architecture shown below, (a) Add component(s) and data path(s) to support instruction " j " (unconditional jump). 5% (b) Add component(s) and data path(s) to support instruction "jal" (jump and link). 5% (c) Add component(s) and data path(s) to support instruction "slt" (set on less than) 5% 2. Explain the following terminologies using your own ways. 10% (a) Page table register (b) Valid bit, Dirty bit and Reference bit (c) Loop unrolling (d) Compulsory misses and Conflict misses (e) Write-through and Write-back 3. Determine and explain why the following statement is true or false. 30% (a) Predicting "taken" for the backward branches is good. (b) The OS should clear all "dirty bits" to zero periodically. (c) Pipelining can reduce instruction latency because of parallel processing. (d) To apply LRU, we need to record the "reference bit". (e) Page table is implemented with SRAM. (f) TLB is greater than a typical cache