1. Explain why DRAM memory requires refreshing. 2. What are the differences between write-back and write through? 3. Suppose a memory system has four banks, each of which has a latency of 200 ns and is pipelined to allow 8 operations to overlap execution. If each bank returns 4 bytes of data in response to a memory request, what is the peak throughput and peak bandwidth of this system? What is the bandwidth of a memory system that transfers 32 bits of data per request, has a latency of 30 ns per operation, and has a precharge time of 5 n:s between operations? 4. 5. Suppose a DRAM has a RAS-CAS delay of 40 ns, has a CAS-data delay of 25 ns, and requires a precharge time of 10 ns. If the DRAM does not support page mode and returns 4 bits of data from each memory reference, what is its latency for read operations, throughput (assume reads and writes take the same amount of time), and bandwidth? IF a DRAM has a 256 rows, and its refresh time is 10 ms, how often (on average) does a row refresh operation need to be done? 6. What are the hit and miss rates in the cache and the main memory if the processor executes a total of 1,500,000 memory references, , 1200,000 of which hit in the cache and 300,000 of which hit in the main memory 7