1. Question in Computer Architecture.

(c) Assume that the following instruction has to be executed in a hypothetical computer. SUB RI, [X] X is a indirect memory address which contains the address of data. This instruction is available in memory location Y. Identify the microoperations required to execute this instruction, involving fetch cycle, indirect cycle and execute cycle. (3 marks) (d) Assume that in a multiprocessing environment, data X is available in main memory. If this data is brought into local cache memory of three processors (P1,P2,P3), briefly explain how the cache coherence problem can occur with an illustration. (2 marks)