1. Show how the following four instructions move through each stage of the five stage pipeline, similar to the example on slide 11 of lecture 17. This pipeline does support bypassing. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved. You don't need to show the latch involved in every bypass (but feel free to ponder this question for your own understanding). (40 points) I1: add $s1, $s2, $s3 I2: lw $s4, 8($s2) I3: add $s5, $s4, $s1 I4: sw $s5, 8($s2)

2. Consider an in-order pipeline that has the following stages. Unlike the example in class, a register read takes an entire cycle and a register write takes an entire cycle (not a half cycle).

Fetch	Decode	Regread	IntALU	Regwrite
			IntALU	Datamem	Datamem	Regwrite

After instruction fetch, the instruction goes through a separate Decode stage where dependences are analyzed, then a separate Regread stage where input operands are read from the register file. After this, an instruction takes one of two possible paths. Int-adds go through the stages labeled "IntALU" and "Regwrite". Loads/stores go through the stages labeled "IntALU", "Datamem", "Datamem", and "Regwrite", i.e., it takes two cycles to retrieve data from the data memory unit. How many stall cycles are introduced between the following pairs of successive instructions (i) for a processor with no register bypassing and (ii) for a processor with full bypassing? (60 points)

1. add $1, $2, $3 add $4, $1, $5

2. lw $1, 8($2) lw $3, 8($1)