[10/10/10] For each part of this exercise, assume that initially all caches lines are invalid, and the data in memory Mi is the byte 1 (0X00 C3: R, M4 - C3: R, M2 C1: W, M40xbbbb C3: R, MO C3: R, M2 C6: W, M4 For each part of this exercise, assume that initially all caches lines are invalid, and the data in memory Mi is the byte 1 (0X00 C3: R, M4 - C3: R, M2 C1: W, M40xbbbb C3: R, MO C3: R, M2 C6: W, M4