11. I The latencies of the components of the single-cycle datapath are: Memory Read: 6 ns Memory Write: 10 ns Register file: 3 ns ALU: 4 ns (all other components have negligible latency) a) If the clock-cycle time is made as small as possible, what is the clock frequency? b) Assume a program with instruction mix of 23% loads, 13% stores, 19% branches, 2% jumps, 43% ALU, what is the average clock cycle time for this program? c) We have to choose between two performance optimizations: either a new ALU (latency 3 ns) or a new register file (latency 2 ns). Which would be a better choice? Justify your