2. (60 pts) Assume a 7 stage, scalar (1-wide) in-order MIPS pipeline with stages: FT, FA, D, E, MT, MA, W. [Aside: assuming that each memory stage has been split in two for serialized tag check and data access in the I and D caches] Assume full forwarding networks. Indicate stalled instruction occupancy in a pipeline stage with a lower case letter (ft,fa,d,e,mt,ma,w). Assume that all hazard detection and stall insertion logic is in decode (D). Indicate, by drawing an arrow when a value is forwarded from one instruction to another in the cycle that the forwarding occurs. Assume that all loads and stores are hits and that there are no exceptions. Assume that there are zero branch delay slots and perfect branch prediction. Consider the following sequence of instructions (you may assume them to be the inner body of a FOR loop with the initialization code elided) scheduled on the above pipeline, assuming the next dynamic instance of the instruction at label I will be a taken branch.

A: lw $2, 40 ($10)

B: lw $3, 40 ($11)

C: add $5, $4, $2

D: sub $6, $3, $5

E: mul $3, $6, $3

F: sw $3, 0 ($10)

G: addi $10, $10, -64

H: addi $11, $11, -64

I: beq $10, 1024, A

(a) Build a table where there is one row for each instruction and one column for each cycle, starting with the tag check on the fetch of the instruction at label A. Fill in the table with the stage currently occupied by the instruction in that row in that cycle until the instruction beq instruction reaches the writeback stage.

(b) Assuming that all registers other than 0 (fixed), 1 (reserved), 5 (input), 6 (input), and 7(input) and 31(reserved) are freely available for use and that the above sequence can be unrolled by 2x, unroll the above loop and schedule 2 iterations on the same pipeline. Build a similar table (compared to Question 6 in HW1) where there is one row for each dynamic instruction and one column for each cycle. Fill in the table with the stage currently occupied by the instruction in that row in that cycle. What is the cycles/iteration?

(c) Consider a 3-wide VLIW pipeline with the following restrictions: Each bundle includes at most 1 control instruction, at most 2 ALU instructions, and at most 2 memory operations. Assume that the same register restrictions as in 2(a) apply. Assuming that the pipeline has the same stages, forwarding and hazard detection support as in 2 (above), generate a sequence of VLIW Bundles from the unrolled code in 2b and schedule them. How do the cycles/iteration compare with 2(a)?