2. ABCD adder that adds four BCD digits and produces a sum digits in BCD is shown in the figure below. a) Write a Verilog model that describes this BCD adder in structural style using Verilog HDL primitives. b) Write a Verilog model that describes this BCD adder using Verilog HDL data flow modeling c) Write a test bench and use Modelsim to verify if the models in 1.a and 2.b work as four BCD digits adder. (Test bench and simulation are required to verify the BCD adder functionality) b7b6b5b4 a7a6 as a4 b3b2b1b0 a3 a2 a1a0 1111 4-bit binary adder S3 S2 S1 So 4-bit binary adder S3 S2 $1 $o Carry In Carry Out 4-bit binary adder S3 S2 91 $0 4-bit binary adder S3 S2 $1 $0 D7 D6 D5 D4 D3 D2 D1 DO