$2.$ Answer$/$complete the following questions on multiplexers:

$-$ What is the purpose of a mux $($what does it allow you to do$)?$

$\backslash (\backslash$cdot $\backslash )$ For a $64-$input mux, how many selection bits would you need?

$-$ Draw the digital logic for a standard $($no need to minimize circuitry$)4-$input mux. As needed, use notation D$0,$ D$1,$ etc. for data inputs bits and A$,$ B$,$ C$,$ etc. for selection bits.

$3.$ Answer$/$complete the following questions on decoders:

$-$What is the purpose of a decoder $($what does it allow you to do$)?$

$-$ For a decoder with $5$ selection bits, what is the maximum number of data outputs the decoder will enable $($set to $1)$ at any given time?

$-$ Draw the digital logic for a standard $($no need to minimize circuitry$)2-$input decoder.

As needed, use notation D$0,$ D$1,$ etc. for data outputs and A$,$ B$,$ C$,$ etc. for the input$/$selection bits.

$4.$ You've seen a $1-$bit full adder that adds TWO NUMBERS $($A and B$).$ Now, assume you want to implement a $1-$bit full adder that adds THREE NUMBERS $($A$,$ B and C$).$ You will need two carry bits to implement this successfully $($ChiClo$)$ instead of the normal single Cin bit $($HINT: with a $2-$input full adder, you can have $\backslash (1+1+1\backslash )$ input, which would yield a sum of $1$ with carry of $1$ ; a $3-$input full adder can have $\backslash (1+1+1+1\backslash )$ which would yield a sum of $0$ with carry of $2[$binary$=10]).$

$-$ Complete the truth table for the above circuit:

Inputs

Use the least amount of logic gates possible to implement each of the outputs above $($use whatever method works best $[$ingenuity$,$ SoPs, k$-$maps, etc.$)$; assume you can use $2-,3-,4-$input gates etc. with no issue:

Output Sum Output CoutHi Output CoutLo Minimized Circuit:

HINT: You can do this with a single gate.

Minimized Circuit:

HINT: You can do this with a single gate.

Minimized Circuit:

HINT: Best to just use a K$-$map here. You may need more room...draw above if so$.$