2. Connect SN 74LS74AND Flip Flop to the set. For connection use Figure 5.2. DO NOT FORGET to connect Vcc and Ground pins of Flip Flop. PRE is equal to SET and CLR is equal to RESET. CLK should be connected to TTL Pulse OUT. Connect Q and 7 to the Logic Indicator. Realize the truth table according to the inputs in Table 5.2 Table 5.2 D Flip Flop Function ICQUvcc. FUNCTION TABLE 102 132CR 1CLK 12520 OUTPUTS PRE 1 PRE 12CLK 10gs 102PRE ogs GND H Figure 5.2 D Flip Flop 0 a H D X X X H 20 3620 INPUTS CLR CLK H X L X x H + H + H L H L H H Mt H H X Q0 Istanbul Kemerburgaz University Departmant of Electrical and Electronics Engineering EE-244 Digital Systems Laboratory 1 5.5 QUESTIONS 1. What is the difference between latch and flip flop? 2. What is sequential circuit? 3. Give some information about D Flip Flop. 4. Draw D Flip Flop and give the outputs of the gates (every gate) for some inputs. 5. Why do we need Edge-Triggered D Flip-Flop