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2. Consider the single cycle processor diagram: Control MemtoReg Unit MemWrite Branch 00 CLK A PCSrc ALUControl20 31:26 Op ALUSrc 5:0 Funct RegDst RegWrite

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2. Consider the single cycle processor diagram: Control MemtoReg Unit MemWrite Branch 00 CLK A PCSrc ALUControl20 31:26 Op ALUSrc 5:0 Funct RegDst RegWrite CLK CK WE 25:21 A1 WE3 SrcA Zero RD1 RD Instr ALUResult ReadData Instruction 20:16 A2 RD2 SrcB Memory A3 Register WriteData A RD Data Memory WD WD3 File 20:16 15:11 WriteReg4:0 PCPlus4 Signlmm 15:0 < <

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