$2.$ Download and extract the enclosed files from hw$2$a$.$zip:

$$ full$\_$adder$\_$nodelay.v $$ a full one$-$bit adder module

$$ four$\_$bit$\_$adder$\_$subtractor.v $$ a $($broken$)$ four$-$bit ripple$-$carry adder$/$subtractor$,$ which uses

the adder in the above file

$$ adder$\_$subtractor$\_$test.v $$ a test bench that will verify the behavior of the above module

To run the test bench, compile adder$\_$subtractor$\_$test.v and run the resulting binary in the simulator. View the resulting waveform in a waveform viewer. The following commands will do it:

iverilog $-$o adder$\_$subtractor$\_$test $.$ vvp adder$\_$subtractor$\_$test $.$ v

vvp adder$\_$subtractor$\_$test $.$ vvp

The resulting file adder$\_$subtractor$\_$test.vcd is your waveform. To view the waveform, use one of

these options:

$$ If you$$re using Vital or Anubis with Webtop, you can open it using the command

gtkwave adder$\_$subtractor$\_$test.vcd$.$

$$ Alternatively, you can open the file on this website.