2. Draw the state diagram of the machine described by the following Verilog module:

module state_machine(x_in, clk, reset);

input x_in, clk, reset;

reg [1:0] state, next_state;

always @ (poseedge clk, negedge reset)

begin

if (reset == 1b0)

state <= 2b00:

else

state <= next_state:

end

always @(state, x_in)

begin

case (state) 2b00:

begin

if (x_in)

next_state = 2b10;

else

next_state = 2b00;

end

2b01: begin

if (x_in) next_state = 2b10;

else next_state = 2b00;

end

2b10: begin

if (x_in)

next_state = 2b11;

else

next_state = 2b10;

end

default: next_state = 2b01;

endcase

end

endmodule