2 Suppose we have a VLIW that could issue two memeory references, two FP operations, one integer operation or branch in every clock cycle. Consider the loop Loop: l.d f0,0(r1) add.d fo,f0,f2 add.d f0, f0,f0 l.d f4,0(r2) add.d f6,f0,f4 add.d f8,f6,f6 s.df8, 0(r1) addi r2,r2,#-8 addi r1,r1,#-8 bnez rl,Loop Unroll the loop 7 times and schedule it with the minimum number of cycles to execute. Ignore delayed branches