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2. Suppose you have a single-word cache containing 16 blocks. Each memory address is represented as 6 bits. Find out whether the following memory accesses

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2. Suppose you have a single-word cache containing 16 blocks. Each memory address is represented as 6 bits. Find out whether the following memory accesses will be hits/misses. Also show the final state of the cache. [6] 22, 46, 27, 48, 19, 22

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