$2.$ The logic latencies for individual stages in a processor are listed in the

following table.

IF ID EXE MEM WB

$320$ ps $310$ ps $500$ ps $370$ ps $270$ ps

$($a$)$ What is the minimum clock period for a pipelined and a non$-$pipelined

processor using these parameters?

$($b$)$ Assuming the pipeline latencies from part $($a$),$ what is total latency of an

Arm ldur instruction in a pipelined processor? What is the throughput of a large

series of ldur instructions with no stalls or hazards? Express your answer in

millions of instructions per second $($MIPs$).$