2. Write a Verilog program which models the circuit shown below and stimulate with the stimulus pattern used in problem 1. Assume that the rise time and fall time delays for the D flip-flop ou tputs are 14 ns and 20 ns, re spectively, from appropriate changes on the clear or clock. Please use the Verilog submodule named dff_7474 to implement the 7474 flip- flops (you do not need to develop this m odel). Assume that the rise time and fall times for the AND and OR gates are those used in EE 2181 lab #08 "Set-Reset Latch" for the 7400 TTL Logic Family. Please provide a copy of your Verilog program and a graphical timing diagram showing CL, CK, QA, QB and QC. You can also include the the AND and OR logic gates if you wish. You can set the time scale to 1 ns (sets the delay #1 to 1 ns) by inserting at the top of your verilog program the command: 'timescale Ins/lns U1A QA CLK 7474 U1B QB CLK 7432 7474 U2A QC 7432 CK 7408 CLK 1 7474 CL 2. Write a Verilog program which models the circuit shown below and stimulate with the stimulus pattern used in problem 1. Assume that the rise time and fall time delays for the D flip-flop ou tputs are 14 ns and 20 ns, re spectively, from appropriate changes on the clear or clock. Please use the Verilog submodule named dff_7474 to implement the 7474 flip- flops (you do not need to develop this m odel). Assume that the rise time and fall times for the AND and OR gates are those used in EE 2181 lab #08 "Set-Reset Latch" for the 7400 TTL Logic Family. Please provide a copy of your Verilog program and a graphical timing diagram showing CL, CK, QA, QB and QC. You can also include the the AND and OR logic gates if you wish. You can set the time scale to 1 ns (sets the delay #1 to 1 ns) by inserting at the top of your verilog program the command: 'timescale Ins/lns U1A QA CLK 7474 U1B QB CLK 7432 7474 U2A QC 7432 CK 7408 CLK 1 7474 CL