2. Write three differences between a RAM and a ROM. 3. Write three differences between Harvard and Princeton architectures. 4. Consider an SRAM device with address range 05COO to 05FFF. a. Design a memory address decoder for this SRAM device using only maximum 4-input AND/NAND gates b. How many address lines are required for the SRAM? c. Find the capacity of the SRAM. d. Draw a block diagram of the SRAM interfaced with a CPU having 16 address lines and 8 data lines. Also show where the memory address decoder fits in the diagram. Show all power pins, address pins, data pins, and control pins, and label all input and output pins clearly. 5. Find the number of address and data lines for 256 MB RAM memory device. Also, draw a block diagram showing all power pins, address pins, data pins, and control pins. 6. For the memory decoder shown, find the range of addresses and the memory capacity. 7. Draw the flowchart of the CPU execution cycle and describe what happens in each stage of the cycle. 8. Draw the timing diagram of the memory read and memory write operations