[25 pts] 3. Consider the following hypothetical 1-address assembly instruction called Add Then Store Indirect with Pre- increment" of the form ATS + (x) ; M[x] + M[x] +1, M[M[x]] + AC+M[M[x]] The instruction will operate using indirect addressing (as illustrated in Figure 2.4a from the textbook). Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a TEMP register (as shown below). The fetch cycle has been provided below. Give the sequence of microoperations required to implement the execute cycle for the above ATS + (x) instruction. Be sure to combine multiple register transfer operations into the same microcycle when possible. A correct execute cycle solution should consume no more than 9 microoperations. Assume an instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits, and IR is 4 bits. Note that the original content of AC should be preserved. Assume PC is currently pointing to the ATS instruction and only PC and AC have the capability to increment/decrement themselves. ALU AC TEMP Internal Data Bus IR +1 PC MDR MAR CU Internal Control Signals To/from memory and I/O devices External Control Signals Fetch Cycle Cycle 1: MAR PC; Cycle 2: MDR M[MAR], PC +PC+1 Cycle 3: IR MDR.pcode, MAR MDRadd ; Read instruction & increment PC address