2.7 The VHDL structural description of a circuit is shown below. Derive the block diagram according to the code. library ieee; use eee. std logic.1164 . all; entity hundred_counter is port clk, reset: in std.logic; en: in std.logic; q-ten, q.one: ou std logic.vector (3 downto o) pten: out std.logic )i end hundred.counter architecture str arch of hundred.counter is component dec counter port clk, reset in std logic; en: in std_logic; q: out std.logic.vector (3 downto 0) pulse: out stdlogic end component; signal p.one, P-ten: stdlogic: begin one digit: dec_counter (clk=>clk, port map resets)reset, enz)en , pulse-> P-one , q=>9-one) ; ten digit: dec.counter port map (clk->clk, reset->reset, en->p one, pulse->p.ten, q->q-ten); end str-arch