$(3)(20$pts$)$ Assume the $3-$state FSM in problem $(2)$ is correctly implemented as the VHDL entity FSM$.$ You must

complete VHDL Test Bench code for the entity FSM to go through every state transition at least once in this state

sequence for $8$ clocks:

$ACCABCABC$

$($a$)$ The FSM is started in state A in the entity FSM$.$ List a binary sequence on input $W$ for $8clk$ edges to get

exactly the state sequence above and to go through every state transition:

$W=$

$($b$)$ Complete the following VHDL Test Bench code. The declaration of the component FSM is already filled in to

show the I$/$O ports for the entity FSM$.$

Fill in the Test Bench signal declarations. Use the same names as the FSM I$/$O ports. Initialize all signals to $0.$

Fill in the uut instantiation.

Complete the clock$\_$process and the W$\_$process. The simulated clk must be $10MHz.$

PLEASE ANSWER ALL PARTS