3. [4 marks] Oddly-lengthed Stages

Instruction execution design might not always result in stages that are equal in length.

As an example, consider a system that can be cleanly divided into 6 stages, in the order (A, B, C, D, E, F ), each with a propagation delay (in ps) of (110, 220, 190, 200, 100, 80), for a grand total of 900 ps.

The register loading time is 25 ps.

(a) [1 mark] If you only had one extra set of registers to place between an adjacent pair of stages in order to form a 2-stage pipeline, where would you place them? Compute the minimum clock cycle time and the maximum possible CPU throughput.

(b) [1 mark] If you had two extra sets of registers, where would you place them to form a 3-stage pipeline? Again, compute the min clock cycle time and max throughput.

(c) [1 mark] If you had five extra sets of registers, and created a 6-stage pipeline, what would the min clock cycle time and max throughput be?

(d) [1 mark] Suppose you had two extra sets of registers, like in part (b). If you could direct your de- signers to divide any of A, B, C, D, E, F into two stages, where would you tell them to concentrate their efforts?

Reducing Cycle Times Strategy: Divide each assembly instruction into stages Five Stages: 1. fetch (F) 2. decode (D) 3. calculate (C) 4. memory (M) 5. write back (W) Dosave on each have to do al hme The Five Stages e fetch (F) Some upgrades to the ISA: e machine is 2-operand o load next instruction e decode (D) e opcode is 8-bit o prepare operation (hnction select) o load all operands save copy of the current instruction ecalculate (C) save intermediate calculations isters memory (M) access extemal memory (read/wrie) write back (W)