3. A computer has five-stage pipeline, similar towhat we discussed in pipelined implementation of ANNA microarchitecture. Assume the computer deals with control hazards by stalling the pipeline for four cycles immediately after hitting a branch instruction. (There is no special hardware to resolve the branches faster.) Assuming the only source of stalls in this pipeline is control hazards and 30% of all program instructions are conditional branches; assuming CPI without stalls is two, answer the following:(15 + 15)

A.What would be the average CPI (Cycles per Instruction) for this computer?

B.What would be the CPI if we use a nave branch predictor which always assumes that the branch will not be taken and continues fetching the sequentially following instructions. Assume each branch is taken 60% of the time and not taken 40% of the time.