3 Examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions.

For problems in this exercise, assume the following latencies (in ps) for logic blocks in the datapath. (write the actual values from Excel below the variables) CPU Architecture I-Mem Add Mux ALU Regs D-Mem Sign-Ext Shift Left ps D E F G H I J K i) What is the clock cycle time if the only types of instructions we need to support are ALU instructions (ADD, AND, etc.)? ii) What is the clock cycle time if we only have to support LW instructions? iii) What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? For the following distribution of instructions, and with no Pipeline Stalls, please answer the questions following the table below: ADD ADDI NOT BEQ LW SW 20% 15% 0% 25% 25% 15% iv) In what fraction of all cycles is the data memory used. v) In what fraction of all cycles is the input of the sign-extend circuit needed? What is this circuit doing in cycles in which its input is not needed? vi) If we can improve the latency of one of the given datapath components by 10%, which component should it be? What is the speedup from this improvement?

A B D E F G H 6 14 2 280 130 20 150 145 320 15 10 0 - 1 40 1200 1 K L M N zo -- 2