3. For the following figure, all the D flip-flops have setup time as 2ns, hold time as 4ns, telk-q-min = 9ns and telk-q-max = 11ns. a) Assuming clock period as 25ns, determine (by using setup equation) if the circuit has setup violation. If there is set up violation, what should be the value of clock period to avoid setup violation. b) Determine (by using hold time equation), if the circuit has hold time violation. [4] c) Modify (and redraw) the circuit without removing any buffers, such that it works at clock period of 25ns and does not have any timing violations. (Assume only two buffers, with min delay of 6ns and max delay of 8ns, are available). Show clear steps/methodology used for arriving at the violation free circuit. [12] Clk- D A >Clk Q tmin=6ns tmax=8ns D Q B >CIK tmin =6ns tmax=8ns D C >Clk Q