(a) Draw the organization of an 8 × 8 array multiplier and calculate how many full adders, half adders, and AND gates are required.

(b) Highlight the critical path in your answer to (a). (If there are many equivalent ones, highlight any one of them).
(c) What is the longest delay in an 8 × 8 array multiplier, assuming an AND gate delay is t_g = 1 ns, and an adder delay (full adder and half adder) is tad = 2 ns?
(d) For an 8-bit × 8-bit add-and-shift multiplier, how fast must the clock be in order to complete the multiplication in the same time as in part (c)?