3. In Chapter 4, we covered the performance of CPU, bus, and memory on an embedded platform. Let's design a game controller with 4K display at 60 Hz. The standard 4K resolution is 3840 x 2160 pixels Considering the horizontal and vertical blanking, the raw pixels per frame is about 8,754,680. Each pixel is 24 bits that are encoded to 30 bits using TMDS encoding (8/10 bit encoding) (a) What effective date rate is required to transfer video data on the bus? (b) Without considering the bus overhead, what is the minimum bus clock rate for 16-bit bandwidth? (c) Typically PCIe data are transferred as packets. The overhead for each packet is 28 bytes. The payload size can be 0 to 4096 bytes, Giving the PCIe clock speed at 2.5 GHz (or 2.5 GT s per line), what will be the minimum payload size for each packet in order to transfer the 60Hz 4K stream video? 3. In Chapter 4, we covered the performance of CPU, bus, and memory on an embedded platform. Let's design a game controller with 4K display at 60 Hz. The standard 4K resolution is 3840 x 2160 pixels Considering the horizontal and vertical blanking, the raw pixels per frame is about 8,754,680. Each pixel is 24 bits that are encoded to 30 bits using TMDS encoding (8/10 bit encoding) (a) What effective date rate is required to transfer video data on the bus? (b) Without considering the bus overhead, what is the minimum bus clock rate for 16-bit bandwidth? (c) Typically PCIe data are transferred as packets. The overhead for each packet is 28 bytes. The payload size can be 0 to 4096 bytes, Giving the PCIe clock speed at 2.5 GHz (or 2.5 GT s per line), what will be the minimum payload size for each packet in order to transfer the 60Hz 4K stream video