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4. Assuming the single-cycle datapath below, tell me which control signals are asserted for each of the following instructions (a) add (b) addi (c) lw

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4. Assuming the single-cycle datapath below, tell me which control signals are asserted for each of the following instructions (a) add (b) addi (c) lw (d) beq (e) push (new) (f) submi (new) PCSro Add ALU Shif left 2 Instucton (2521] Re Read PC-adress | pow |Read dat.1- instructor, po Zoro ALUALUA 31:0) nstruction Instruction 15:11regster M Wrte Read data 2 resut tAddress Read WriM atas Registers Data Writs memory data instruction (15 0 Sign 32 ALU coneci Instruction (5 0 4. Assuming the single-cycle datapath below, tell me which control signals are asserted for each of the following instructions (a) add (b) addi (c) lw (d) beq (e) push (new) (f) submi (new) PCSro Add ALU Shif left 2 Instucton (2521] Re Read PC-adress | pow |Read dat.1- instructor, po Zoro ALUALUA 31:0) nstruction Instruction 15:11regster M Wrte Read data 2 resut tAddress Read WriM atas Registers Data Writs memory data instruction (15 0 Sign 32 ALU coneci Instruction (5 0

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