$4-$bit ALU

Design and implement in Verilog a $4-$bit ALU using gate$-$level modeling. It should take two $4-$

bit inputs A and $B,$ and produce a $4-$bit output Result by performing $5$ different operations

according to its $3-$bit control input as defined in the following table.

In addtion the ALU should have two other outputs $-$ zero and overflow, defined as follows:

zero $=\{\begin{array}{ccc}1,& if\text{R}\text{e}\text{s}\text{u}\text{l}\text{t}& =0\end{array}$

$0,if$ Result $0$

overflow $=\{\begin{array}{ccc}1,& ifan\text{o}\text{v}\text{e}\text{r}\text{f}\text{l}\text{o}\text{w}\text{o}\text{c}\text{c}\text{u}\text{r}\text{s}on\text{o}\text{p}\text{e}\text{r}\text{a}\text{t}\text{i}\text{o}\text{n}\text{s}\text{A}\text{D}\text{D}\text{,}\text{S}\text{U}\text{B}\text{,}or& SLT\end{array}$

$0,$ otherwise $(no$ overflow $or$ operations AND,$OR)$

Design and imlement the ALU as described in lecture Designing an ALU. Use hierarchical

design and create three different modules: $1-$bit ALU for bits $0-2,1-$bit ALU for bit $3,$ and a $4-$bit

ALU that uses the instances of the first two. See ALU$4-$behavioral.vl for the inputs$/$outputs and

functionality of your ALU. It should work exactly in the same way as

ALU$4-$behavioral.vI and

may be tested with the same test module, however it should be implemented entirely at gate$-$

level.

Documentation and submission: Submit a single report file $($MS Word, PDF$)$ as an

attachment to this assignment. The report should include:

Descriptive text $($ALU operations, operation codes, inputs and outputs$)$

Logic diagrams for each module $(1-$bit ALU for bits $0-2,1-$bit ALU for bit $3,$ and $4-$bit

ALU$).$ Use block$-$level diagrams for the adders and multiplexers. In the logic diagrams

label each module I$/$O with the variable name used in the Verilog code.

Verilog source code of all modules including the test module.

Simulation results $($output from running the compiled Verilog code with the test module$).$

The simulation should show the performance of the ALU for all operations $($AND$,$ OR$,$

ADD, SUB, SLT$).$ For this purpose include a copy of the test module output showing a

few typical examples for each operation, including Overflow and Zero. Label the columns

for the inputs and outputs and print the data inputs and outputs in both binary and signed

decimal format. You may use the test module from ALU$4-$behavioral.vl$.$

When i say gate level, i want the code to follow the format of this example code for a $2$ to $1$ line multiplexer:

module mux$2$to$1($out$,$x$,$y$,$z$)$;

input x$,$y$,$z; $//$Input ports.

output out; $//$Output ports.

wire z$1,$a$,$b; $//$Internal variables.

and and$\_1($a$,$x$,$z$1)$;

and and$\_2($b$,$y$,$z$)$;

not n$1($z$1,$z$)$;

or or$\_1($out$,$a$,$b$)$;

endmodule