4. MIPS ISA: Assume data (5D4C3B2A)hex and (A4B3C2D1)hex are stored in memory at address 0 and 4 , respectively. Consider the following 3 consecutive instruction executions: lw \$t1, 3(\$zero); sw \$t1, 2(\$zero); lw \$t2, 4(\$zero); (a) Show the final contents of $t1 and $$2 in hex number. (b) How many memory accesses are made? (c) Write a MIPS assembly code for negating \$ 12