4) Parity Design Circuit. 15 pts. a) Design a circuit that will give a "" if the four data lines into the circuit have an ODD parity. You may use any combination two input coincidence gates and/or two input exclusive OR gates. b) Redesign the circuit replacing the coincidence and exclusive OR gates with any combination of invertors, two input NAND and two input NOR. c) Each NAND, NOR or invertor has a 10nS propagation delay. Determine the worst case delay