4 points) For the following Verilog description of a 2-input NAND gate, the input signal is switched from Al,B to (Al,B 10, please tell the maximum delay of the output signal switching. module myNAND(O, A1, B1) input A1, B1; output O; nand( O, A1, B1 ); specify specparam T1 1:3:5 T2 = 2:46; (A1 >o) (T1, T2 ); (BI=>O) = ( T2, T1 ); endspecify endmodule