4. Use a timing diagram to illustrate how metastability can yield incorrect output for the secure car key controller of Figure 3.69. Use a second timing diagram to show how the synchronizer flip-flop introduced in Figure 3.84 may reduce the likelihood of such incorrect output. Hint: Study the truth table to see which flip flops are affected by a. Without a synchronizer: Clk a S2 S1 50 r With a synchronizer: Clk a Synchronizer S2 S1 SO clk- a Combinational n2 logic n1 no $2 s1 s0 State register Figure 3.69 Secure car key controller architecture. Original flip-flop Combinational n2 logic n1 no $2 $1 s0 clk- State register Figure 3.84 Secure car key controller extended with D flip- flop on asynchronous input to reduce chances of metastability problems.