4.0 D Flip-Flops Refer to Section 5.4 for a detailed explanation of D Flip-Flops In a new project, labstep3?, use the Gated D Latch you built to design a Negative-Edge- Triggered Master-Slave D Flip-Flop. Section 5.4.1 discusses this design. Refer to Figure 5.9a. Use the DE2-115 board to observe the behavior of the latch. When you are convinced that the latch is performing as predicted, and you are confident you understand its behavior, complete the timing diagram on the answer sheet, (pulse your clock signal once with D low before you start), and demonstrate your circuit to the TA. In a new project (lab9step3b) you will design a Positive-Edge-Triggered D Flip-Flop using NAND gates. Section 5.4.2 discusses this design. Please use Figure 5.11a as a guide for this step. Use the DE2-115 board to observe the behavior of the latch. When you are convinced that the latch is performing as predicted, and you are confident you understand its behavior, complete the timing diagram on the answer sheet, and demonstrate your circuit to the TA