[41 125 pts total] Design a clocked Mealy synchronous FSM that will detect the input sequence X- 1011011 and produce an output Z-1 when the last bit of the sequence is detected. Overlaps can occur and must be handled properly. a [10 pts] Draw the state diagram. Clearly show all input, output and state information b [15 pts Determine the number of memory elements required to implement. Make a state assignment and create the encoded state table