4.31 In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop (written in C): for(i=0;i!=j;i+=2) b[i]=a[i]a[i+1]; A compiler doing little or no optimization might produce the following LEGv8 assembly code:

MOV X5, XZR B ENT TOP: LSL X10, X5, #3 ADD X11, X1, X10 LDUR X12, [X11, #0] LDUR X13, [X11, #8] SUB X14, X12, X13 ADD X15, X2, X10 STUR X14, [X15, #0] ADDI X5, X5, #2 ENT: CMP X5, X6 B.NE TOP

The code above uses the following registers:

i j a b Temporary values X5 X6 X1 X2 X10X15

Assume the two-issue, statically scheduled processor for this exercise has the following properties: 1. One instruction must be a memory operation; the other must be an arithmetic/logic instruction or a branch. 2. The processor has all possible forwarding paths between stages (including paths to the ID stage for branch resolution). 3. The processor has perfect branch prediction. 4. Two instruction may not issue together in a packet if one depends on the other. (See page 345.) 5. If a stall is necessary, both instructions in the issue packet must stall. (See page 345.)

As you complete these exercises, notice how much effort goes into generating code that will produce a near-optimal speedup.

QUESTION:

4.31.3 [10] <4.10> Rearrange/rewrite the LEGv8 code given above to achieve better performance on the one-issue processor. Hint: Use the instruction CBZ X6, XZR, DONE to skip the loop entirely if j = 0. 4.31.4 [20] <4.10> Rearrange/rewrite the LEGv8 code given above to achieve better performance on the two-issue processor. (Do not unroll the loop, however.) 4.31.5 [30] <4.10> Repeat Exercise 4.31.1(below), but this time use your optimized code from Exercise 4.31.4. 4.31.6 [10] <4.10> What is the speedup of going from a one-issue processor to a two-issue processor when running the optimized code from Exercises 4.31.3 and 4.31.4. 4.31.7 [10] <4.10> Unroll the LEGv8 code from Exercise 4.31.3 so that each iteration of the unrolled loop handles two iterations of the original loop. Then, rearrange/rewrite your unrolled code to achieve better performance on the one-issue processor. You may assume that j is a multiple of 4. 4.31.8 [20] <4.10> Unroll the LEGv8 code from Exercise 4.31.4 so that each iteration of the unrolled loop handles two iterations of the original loop. Then, rearrange/rewrite your unrolled code to achieve better performance on the two-issue processor. You may assume that j is a multiple of 4. (Hint: Re-organize the loop so that some calculations appear both outside the loop and at the end of the loop. You may assume that the values in temporary registers are not needed after the loop.) 4.31.9 [10] <4.10> What is the speedup of going from a one-issue processor to a two-issue processor when running the unrolled, optimized code from Exercises 4.31.7 and 4.31.8? 4.31.10 [30] <4.10> Repeat Exercises 4.31.8 and 4.31.9, but this time assume the two-issue processor can run two arithmetic/logic instructions together. (In other words, the first instruction in a packet can be any type of instruction, but the second must be an arithmetic or logic instruction. Two memory operations cannot be scheduled at the same time.)

Exercise 4.31.1: Draw a pipeline diagram showing how LEGv8 code given above executes on the two-issue processor. Assume that the loop exits after two iterations.