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5. correct the error in the Verilog . # 4-bit Adder subtractur module addSub(A, B, sel ; Result); input sel; input [5:0] A,B; output [3:0]
5. correct the error in the Verilog . # 4-bit Adder subtractur
module addSub(A, B, sel ; Result);
input sel;
input [5:0] A,B;
output [3:0] Result;
wire [3:0] result;
assign Result = (sel)? A + B : A - B;
endmodul
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