5-4. The following register transfers are to be executed in the system of Fig. 5-4. For each transfer, specify: (1) the binary value that must be applied to bus select inputs S2, S, and So; (2) the register whose LD control input must be active (if any); (3) a memory read or write operation (if needed); and (4) the operation in the adder and logic circuit (if any). b. IR MIAR] c. M[AR] TR d. AC DR, DR AC (done simultaneously) St Memory unit 4096 16 Write Read LD INR CLR PC LD INR CLR DR LD INR CLR and LD INR CLR INPR IR LD TR LD INR CLR OUTR Clock LD Figure 5-4 Basic computer registers connected to a common bus