7. (10pts) A student has an binary bits, and formats, where 2 encoded using 8 assignment to design a new 8-bit ISA, where every instrucotowin two encoding ow MIPS ISA design by using the following two encoding a new is the number of bits for each field. R-type opcode rs 1- type opcode rs rt func. code immediate The new 8-bit ISA can perform only the following operations: add Srl, Sr2 . # add contents of Sr2 to Srl and put the sum in Sri sub Srl, Sr2 sll Sr1, 2 and Srl,Sr2 addi Srl, Sr2, 1 # add contents of Sr2 with 1 and put the sun in Sri ld Sr1, 0(Sr2) bne Srl, Sr2, label # if contents of Srl does not equal to Sr2, goto label # subtract contents of Sr2 from Srl and put the difference in Sri # shift left contents of Srl by 2 bits and put the result in s # perform AND operation on Srl and Sr2, and the result goes to Sri rl # load contents of memory addressed by Sr2 and put in Sri where the first 4 instructions use R-type format and 2-address source and destination, Sri (i-0, 1,2...) are registers, and SrO is always 0. Addi, ld, and beq use I-type format. architecture (i.ec., one source register is used as both o verify his design, he implemented the following for-loop using the above instructions in the table, where the index i is associated with re gister Sr1, the base address of array A is in Sr2, and sum in Sr3. int sum-; for (int 0 5 i+t) Based on his ISA design, there exists some problems (i.e., violates his design) in some of the instructions of his loop implementation. Find all the instructions that have problem, and identify the problems. If there is a problems for instruction, what is the problem? Instruction addi Sri, sro, sro #i-o add Sr3, sro, sro # sum-0 addi sr2, sro, 5 # biggest index 5 Li: sll Srl, 2 #i*4 add Sr4, Sr2 #base + i+4 Id Sr2, 0(Sr4) # load Alill addi Sr3, Sr2, 4 # sum-A [i1-4 # i-i+1 addi Sri, rl, 1 bne Srl, Sr2, L1 # if ie5 go back |