7.14 In an analog amplifier, the output voltage becomes saturated (i.e., reaching the most positive voltage, +Vec, or the most negative voltage, -Vcc) when the output exceeds the maximal range. In some digital signal processing applications, we wish to design an 8-bit signed saturation adder that mimics the behavior of an analog amplifier; i.e., if the addition result overflows, the result becomes the most positive or the most negative numbers. Draw the top-level diagram and derive the VHDL code accordingly. 7.14 In an analog amplifier, the output voltage becomes saturated (i.e., reaching the most positive voltage, +Vec, or the most negative voltage, -Vcc) when the output exceeds the maximal range. In some digital signal processing applications, we wish to design an 8-bit signed saturation adder that mimics the behavior of an analog amplifier; i.e., if the addition result overflows, the result becomes the most positive or the most negative numbers. Draw the top-level diagram and derive the VHDL code accordingly