87 8 bits Bit 15 8 bits Mantissa (M) is an unsigned fixed-point fraction Exponent(E) is in 2's complement Decimal value (0.M) * 25 Figure 010) (7 marks) Question 2 (25 marks) Figure Q2 shows the characteristics of a hypothetical machine, relevant portions of memory, processor registers and some I/O devices. For the instruction format shown in Figure Q2(0), if it is an I/O instruction, bits 4 to 15 identifies a particular 1/O device, else a memory address. Bit 0 15 Opcode Meanory address of 10 derece number fi) Instruction format 1 Bit o Sian Magnitsde (ii) Integer format Program counter (PC)= Address of wastruction Accumulator (AC) = Temporary storage Instruction register (IR) = Instruction being executed (iii) Internal CPU registers 0010 = Store AC to memor 0011 = Lead AC from 10 0101 = Add to AC from memory (h) Partial list of opcodes 600 601 602 Memory 3009 5888 2889 CPU registers 600 PC . IR 888 889 0008 TO Devices COOB ] Dev 9 (All mumbers are in hexadecimal) (v) Contents of memory, registers and I/O devices at start of program Figure Q2 87 8 bits Bit 15 8 bits Mantissa (M) is an unsigned fixed-point fraction Exponent(E) is in 2's complement Decimal value (0.M) * 25 Figure 010) (7 marks) Question 2 (25 marks) Figure Q2 shows the characteristics of a hypothetical machine, relevant portions of memory, processor registers and some I/O devices. For the instruction format shown in Figure Q2(0), if it is an I/O instruction, bits 4 to 15 identifies a particular 1/O device, else a memory address. Bit 0 15 Opcode Meanory address of 10 derece number fi) Instruction format 1 Bit o Sian Magnitsde (ii) Integer format Program counter (PC)= Address of wastruction Accumulator (AC) = Temporary storage Instruction register (IR) = Instruction being executed (iii) Internal CPU registers 0010 = Store AC to memor 0011 = Lead AC from 10 0101 = Add to AC from memory (h) Partial list of opcodes 600 601 602 Memory 3009 5888 2889 CPU registers 600 PC . IR 888 889 0008 TO Devices COOB ] Dev 9 (All mumbers are in hexadecimal) (v) Contents of memory, registers and I/O devices at start of program Figure Q2