9. (15pts) Answer each of the following with a TRUE (T) or FALSE (F). (1) Data in SRAM will be lost without refreshing frequently (2) A cache is a small fast memory that stores a subset of the information in the memory below it. (3) In set associative cache, a given memory block can be placed in only one place in the cache. (4) The unit of data transfer between cache and main memory is a word. (5) When CPU requests a word and cannot find it in cache, it is called a miss. In this case, the requested word will need to be delivered directly from the main memory to the CPU (6) Virtual memory is a technique of using main memory as a cache for hard drive. (7) If you can find a value x in the cache, you can find it in the main memory too. (8) Set associative caches decrease the miss rate but are slow when the associativity is increased. (9) Keeping everything else constant, increasing the block size always decreases the miss rate. (10) Write-Back and Write-Through differ in whether data will be ultimately written to the main memory or not. (11) Idea pipelined processor has a CPI-1, which is the same as single cycle processor. So they have the same performance. (12) The clock cycle time of a single cycle microprocessor is determined the critical path (lw instruction). _(13) we need to put the most recently used item in cache according to spatial locality. -_(14) Structural hazard is caused by data dependence and data hazard is caused by hardware conflict. (15) A major approach for reducing miss penalty is to use split cache. (10 pts) Suppose there is a direct-mapped cache containing 4 MB (note IM- 220 of data, and each cache block contains 4 words (note: not bytes). Answer the following questions: (a) How many blocks are there in the cache? (b) Show the decomposition of a 32-bit memory address into the appropriate fields (tag, block index and offset). Calculate the number of bits for each field. (c) Calculate the real total size of the cache. Show your work, simply giving an answer is not enough