9. (8pt) For a direct-mapped cache design with a 32-bit address, the Tag 31-10, Index 9-5, Offset 4-0 address are used to access the cache. We assume that there is one valid bit per block a. What is the cache block size (in words)? b. How many entries does the cache have? c. The total bits required for such a cache implementation- words (1 word has 4 bytes) entries there is a valid bit per block.) What is the ratio pure data storage bits. bits. (Recall between total bits required for such a cache implementation over the d. (The answer has to be in the form of 1.xxx)