A$.1$ Fast Constant Multiplier $($There are two pictures, please help finish all the parts$)$

A constant multiplier of fixed point numbers can be implemented by a series of shift$-$and$-$add operation.

In this question, you will design a high performance constant multiplier that implements:

y$=46$ d

where d is an $8-$bit unsigned number in signal d$[7$:$0]$ and y is a $16-$bit unsigned number y$[15$:$0].$

For this question, use the following timing information:

A$\mathrm{.}1\mathrm{.}1$ Your first implementation, called Circuit A$,$ uses the observation that

y$=46$ d$=(2^(5)+2^(3)+2^(2)+2)$d

and implements the constant multiplier as follows:

Draw on the figure above the longest combinational path $($critical path$)$ between the two registers. What

is the combinational delay through this path? Note that the width of the adder $($n$)$ is shown on the

diagram. Also, note that an n$-$bit adder adds two n$-$bit input and produces an $($ n$+1)-$bit output, which

includes the carry out as the most significant bit. You can assume signals that are not wide enough are

padded automatically to fit the correct width. A$\mathrm{.}1\mathrm{.}2$ Taking into account the setup and hold time of the registers, what is the highest clock rate that Circuit $\backslash ($ A $\backslash )$ above can run at$?$

A$\mathrm{.}1\mathrm{.}3$ Instead of decomposing the constant $46$ into the way shown in Part $($a$),$ it may alternatively be decomposed in the following two ways:

$-$ Circuit $\backslash ($ B: $46=\backslash$left$(2^\{5\}+2^\{3\}\backslash$right$)+\backslash$left$(2^\{2\}+2\backslash$right$)\backslash )$

$-$ Circuit $\backslash ($ C: $46=2^\{6\}-2^\{4\}-2\backslash )$

Note the grouping of operation above and how they may affect the order of computation. Also, you can assume you can use the adder for subtraction, which will incur the same delay. Based on the above $2$ different ways of decomposing the constant $46.$ In the following space, sketch the two circuit $($Circuit $\backslash ($ B $\backslash )$ and $\backslash ($ C $\backslash ))$ that correspond to the two decompositions. Both circuits should have only one layer of input and one output register similar to Circuit $\backslash ($ A $\backslash ).$ Clearly label the width of the adder and the width of the buses.

A$\mathrm{.}1\mathrm{.}4$ Focusing on just Circuit $\backslash ($ A $\backslash ),$ your project partner suggests that using all adders of the same width can result in circuit that runs at the same throughput as ones that run with adders of different width. Is your partner correct? Demonstrate your answer by designing a circuit similar to Circuit $\backslash ($ A $\backslash )$ but by using only adders of the same width. Clearly label the width of your adders. What is the maximum circle that this circuit may operate at$?$

A$\mathrm{.}1\mathrm{.}5$ Based on the above observations, either by designing a new circuit typology yourself $($as circuit D$),$ or by using the above Circuit A$,$ B$,$ C$,$ with optional pipeline registers inserted, construction $2$ designs: $($i$)$ with highest throughput, and $($ii$)$ with lowest latency.