a) (1.5 marks) The following Verilog code consist of an error. Find the error and show how you can fix it module reg_2b_lda_ldb (q,a,b,lda, 1db, clk) parameter N2i input [N-1:0] a, b; input lda, ldb, clk output N-1:01k always (posedge clk) if (lda1'b1) begin q = a; end else begin if (ldb1'bl) q-bi end endmodule b) (3 marks) Draw a circuit that implements the previous Verilog code (assuming the error is irrelevant) using gates and D-CE flip-flops. c) (3 marks) Show how your circuit can be simplified if Ida ldb 1'bl can never occur. Use MUXes and D-CE flip-flops in your simplified circuit. a) (1.5 marks) The following Verilog code consist of an error. Find the error and show how you can fix it module reg_2b_lda_ldb (q,a,b,lda, 1db, clk) parameter N2i input [N-1:0] a, b; input lda, ldb, clk output N-1:01k always (posedge clk) if (lda1'b1) begin q = a; end else begin if (ldb1'bl) q-bi end endmodule b) (3 marks) Draw a circuit that implements the previous Verilog code (assuming the error is irrelevant) using gates and D-CE flip-flops. c) (3 marks) Show how your circuit can be simplified if Ida ldb 1'bl can never occur. Use MUXes and D-CE flip-flops in your simplified circuit