A B C F1 A B C F2 A B C F3 1 0 1 0 0 0 1 10 1 1 00 1 1 0 0 Q2A: Truth tables of three logic functions F1, F2 and F3 given above. Implement the function F1, F2 and F3 using 3 to 8 decoder? (Assume a 3to8 decoder component given to you, if required you may use minimum number of additional logic gates to support your design with 3 to 8 decoder) (Points) 3 to 8 Decoder Q2B: Write HDL code to implement the above function F1, F2 and F3. All three function should include in on HDL code. In you HDL code use 8 to 1 decoder as a component and need not write HDL code of the decoder itself. You should provide a HDL program for all three Function F1, F2, and F3 with single Entity and Architecture. (points)