A bus cycle consists of a high phase followed by a low phase. The bus is said to have a 50% duty cycle because its high phase and its low phase consume the same amount of time. During the high clock phase, the address is transmitted and decoded. This takes 20 nano-seconds. During the low clock phase the requested data block is transferred and takes 15 nano-seconds. What is the maximum clock rate for the system if it employs a 50% duty cycle and transmits one 512-byte data block during the low phase of each bus clock cycle? Express your answer in MHz.

Time Clock cycle Bus clock High phase Low phase Address and command X I Data 10 12